module synth( input clock, input start, output synth_in, input synth_out, output rclk, output sck, output sda ); reg i2c_clock = 0; reg [5:0] clock_div = 0; assign synth_in = clock; assign rclk = synth_out; synth_config cfg(i2c_clock, start, sck, sda); always @(posedge clock) begin clock_div <= clock_div + 1; if (clock_div == 0) begin i2c_clock <= ~i2c_clock; end end endmodule