module wola (
    input               clk,
    input               reset,
    input [9:0]         data_in,

    output reg [19:0]    data_out
);

reg [6:0] addr, next_addr;

reg [9:0] hist1[0:127];
reg [9:0] hist2[0:127];
reg [9:0] hist3[0:127];
reg [9:0] hist4[0:127];
reg [9:0] hist5[0:127];
reg [9:0] hist6[0:127];
reg [9:0] hist7[0:127];

reg [9:0] coeff0[0:127];
reg [9:0] coeff1[0:127];
reg [9:0] coeff2[0:127];
reg [9:0] coeff3[0:127];
reg [9:0] coeff4[0:127];
reg [9:0] coeff5[0:127];
reg [9:0] coeff6[0:127];
reg [9:0] coeff7[0:127];

reg [9:0] x1, x2, x3, x4, x5, x6, x7;
reg [9:0] c0, c1, c2, c3, c4, c5, c6, c7;
reg [19:0] p0, p1, p2, p3, p4, p5, p6, p7;

reg [7:0] i;
initial begin
    for (i = 0; i < 128; i = i + 1) begin
        coeff0[i] = 1;
        coeff1[i] = 1;
        coeff2[i] = 1;
        coeff3[i] = 1;
        coeff4[i] = 1;
        coeff5[i] = 1;
        coeff6[i] = 1;
        coeff7[i] = 1;
    end
end

always @(posedge clk) begin
    if (reset) begin
        addr <= 0;
        next_addr <= 1;
    end else begin
        hist1[addr] <= data_in;
        hist2[addr] <= x1;
        hist3[addr] <= x2;
        hist4[addr] <= x3;
        hist5[addr] <= x4;
        hist6[addr] <= x5;
        hist7[addr] <= x6;

        x1 <= hist1[next_addr];
        x2 <= hist2[next_addr];
        x3 <= hist3[next_addr];
        x4 <= hist4[next_addr];
        x5 <= hist5[next_addr];
        x6 <= hist6[next_addr];
        x7 <= hist7[next_addr];

        c0 <= coeff0[next_addr];
        c1 <= coeff1[next_addr];
        c2 <= coeff2[next_addr];
        c3 <= coeff3[next_addr];
        c4 <= coeff4[next_addr];
        c5 <= coeff5[next_addr];
        c6 <= coeff6[next_addr];
        c7 <= coeff7[next_addr];

        next_addr <= next_addr + 1;
        addr <= next_addr;

        p0 <= data_in * c0;
        p1 <= x1 * c1;
        p2 <= x2 * c2;
        p3 <= x3 * c3;
        p4 <= x4 * c4;
        p5 <= x5 * c5;
        p6 <= x6 * c6;
        p7 <= x7 * c7;

        data_out <= p0 + p1 + p2 + p3 + p4 + p5 + p6 + p7;
    end
end

endmodule