module pll_interface(
    input clock,
    input start,
    input [23:0] data,
    
    output reg running = 0,
    
    output pll_le,
    output pll_data,
    output pll_clock
);

reg [1:0] div = 0;
reg [23:0] sr = 0;
reg [4:0] count = 0;
reg int_pll_clock = 0;

wire count_data = (count < 24);
wire count_le = (count == 25);
wire count_end = (count == 26);

assign pll_data = sr[23];
assign pll_le = count_le ? 1 : 0;
assign pll_clock = count_data ? int_pll_clock : 0;

always @(posedge clock) begin
    if (~running) begin
        count <= 0;
        div <= 0;
        int_pll_clock <= 0;
        
        if (start) begin
            running <= 1;
            sr <= data;
        end
    end else if (running) begin
        if (div != 2'b11) begin
            div <= div + 1;
        end else begin
            div <= 0;
            
            // Internal PLL clock
            int_pll_clock <= ~int_pll_clock;
            
            if (int_pll_clock) begin
                count <= count + 1;
                sr <= {sr[23:0], 1'b0};
            end
            
            if (count_end) begin
                running <= 0;
            end
        end
    end
end

endmodule