module pll_config(
    input clock,
    input start,
    
    output busy,
    
    output pll_le,
    output pll_data,
    output pll_clock
);

parameter mux_z =    3'b000;
parameter mux_dld =  3'b001;
parameter mux_n =    3'b010;
parameter mux_high = 3'b011;
parameter mux_r =    3'b100;
parameter mux_old =  3'b101;
parameter mux_sdo =  3'b110;
parameter mux_low =  3'b111;

parameter cfg_mux = mux_dld;   // One of mux_* above

parameter pre_8 =  2'b00;
parameter pre_16 = 2'b01;
parameter pre_32 = 2'b10;
parameter pre_64 = 2'b11;
parameter cfg_prescalar = pre_8;
parameter cfg_cpi = 6'b000000;
parameter cfg_timer = 4'b1000;
parameter cfg_fastlock = 2'b00;
parameter cfg_pd_polarity = 1'b1;   // 0=negative, 1=positive

parameter cfg_ld_precision = 1'b0;  // 0=3 cycles, 1=5 cycles
parameter cfg_backlash = 2'b01;
parameter cfg_r = 14'd512;

parameter cfg_b = 13'd103;
parameter cfg_a = 6'd7;

reg cfg_start = 0;
reg [1:0] state = 0;
reg [23:0] cfg_data = 0;

assign busy = state[0] | state[1];

pll_interface spi(clock, cfg_start, cfg_data, running, pll_le, pll_data, pll_clock);

always @(posedge clock) begin
    case (state)
        2'h0: begin     // Idle
            if (start) begin
                // Function latch with reset
                cfg_data = {cfg_prescalar, 1'b0, cfg_cpi, cfg_timer, cfg_fastlock, 1'b0, cfg_pd_polarity, cfg_mux, 4'b0011};
                cfg_start <= 1;
                state <= 1;
            end
        end
        2'h1: begin     // Write R counter
            if (!cfg_start && !running) begin
                // R counter
                cfg_data = {3'b000, cfg_ld_precision, 2'b00, cfg_backlash, cfg_r, 2'b00};
                cfg_start <= 1;
                state <= 2;
            end else begin
                cfg_start <= 0;
            end
        end
        2'h2: begin     // Write N counter
            if (!cfg_start && !running) begin
                // N counter
                cfg_data = {3'b000, cfg_b, cfg_a, 2'b01};
                cfg_start <= 1;
                state <= 3;
            end else begin
                cfg_start <= 0;
            end
        end
        2'h3: begin     // Done
            cfg_start <= 0;
            if (!cfg_start && !running) begin
                state <= 0;
            end
        end
    endcase
end

endmodule