module chan_sep (
    input clk,
    input reset,
    input [9:0] adc_data,       // Input from ADC or band selection filter
    output debug,
    output [7:0] chan_num,      // Channel number being output
    output [18:0] chan_if_i,    // Channel IF sample, in-phase (real) component
    output [18:0] chan_if_q     // Channel IF sample, quadrature (imaginary) component
);
    //`define TEST_CHANNEL 83

    wire [19:0] wola_data;
    reg [9:0] wola_delay;
    
    // WOLA filter
    //wola wola(clk, reset, adc_data, wola_data);
    assign wola_data[19:10] = adc_data;
    
    // FFT inputs
    wire fwd_inv_we = 0;
    wire fwd_inv = 1;
    reg start = 0;
    wire [9:0] xn_re = wola_data[19:10];
    wire [9:0] xn_im = 0;
    
    // FFT outputs
    wire rfd;
    wire dv;
    wire done;
    wire busy;
    wire edone;
    wire [18:0] xk_re, xk_im;
    wire [7:0] xn_index, xk_index;
    
    `ifdef TEST_CHANNEL
        reg [31:0] test_data;
        
        always @(posedge clk) begin
            if (chan_num == `TEST_CHANNEL) begin
                test_data <= test_data + 1;
            end
        end
        
        assign chan_if_i[18:3] = (chan_num == `TEST_CHANNEL) ? test_data[15:0] : 0;
        assign chan_if_i[2:0] = 2'b00;
        
        assign chan_if_q[18:3] = (chan_num == `TEST_CHANNEL) ? test_data[31:16] : 0;
        assign chan_if_q[2:0] = 2'b00;
    `else
        assign chan_if_i = xk_re;
        assign chan_if_q = xk_im;
    `endif
    
    assign chan_num = xk_index;
    
    // 256-point FFT
    fft256 fft(fwd_inv_we, rfd, start, fwd_inv, dv, done, clk, busy, edone, xn_re, xk_im, xn_index, xk_re, xn_im, xk_index);
    
    assign debug = start;
    
    always @(posedge clk) begin
        if (reset) begin
            start <= 0;
            wola_delay <= 0;
        end else begin
            wola_delay <= wola_delay + 1;
            
            if (wola_delay == 10'h37d) begin
                // Start the FFT here so the first output from the WOLA filter
                // arrives when the FFT's xn_index is 3, which is when it reads
                // the first sample.
                start <= 1;
            end
        end
    end

endmodule